november 2009 ?2005 fairchild semiconductor corporation www.fairchildsemi.com fsusb11 ? rev. 1.0.4 fsusb11 ? low-power, full-speed (12mbps) switch fsusb11 ? low-power, full-speed (12mbps) switch features ? space saving micropak? (1.6 x 2.1mm) ? usb 1.1 signal switching compliant ? 3db bandwidth: >350mhz ? maximum 1.15 ? r on at 4.5v v cc and 4 ? for 2.7v supply ? 0.3 ? maximum r on flatness for +5v supply ? broad v cc operating range: 1.65v to 5.5v ? fast turn-on and turn-off time ? break-before-make enable circuitry ? over-voltage tolerant, ttl-compatible control input applications ? cell phones, pdas, digital cameras, notebook computers description the fsusb11 is a high-performance, dual single-pole double-throw (spdt) switch designed for switching usb 1.1 signals. the device features ultra-low on resistance (r on ) of 1.15 ? maximum at 4.5v v cc and 4.3 ? at 2.7v supply. high bandwidth and ultra low (r on ) make this switch able to pass both usb low- and full- speed signal with minimum signal distortion. the device is fabricated with sub-micron cmos technology to achieve fast switching speeds and designed for break- before-make operation. the select input is ttl-level compatible. ordering information part number operating temperature range eco status package packing method fsusb11l10x -40 to +85c rohs 10-lead, micr opak?, jedec mo255,1.6 x 2.1mm tape and reel fsusb11mtcx -40 to +85c rohs 14-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide tape and reel for fairchild?s definition of eco status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html . figure 1. block diagram micropak? is a trademark of fairchild semiconductor corporation.
? 2005 fairchild semiconductor corporation www.fairchildsemi.com fsusb11 ? rev. 1.0.4 2 fsusb11 ? low-power, full-speed (12mbps) switch pin configuration figure 2. tssop pin assignment (top view) figure 3. micropak? pin assignment (top view) analog symbol figure 4. analog symbol pin descriptions tssop pin # micropak? pin # pin names description 1, 3, 4, 6, 9, 12 1, 3, 4, 6, 7, 9 d+, d 1+ , d-, d 1 -, d 2- , d 2 + data ports 2, 5 10 gnd ground 7, 8 nc no connect 10, 13 2, 8 s 1 , s 2 control input 11, 14 5 v cc supply voltage truth table control inputs function low logic level d 1 connected to d+/d- high logic level d 2 connected to d+/d-
? 2005 fairchild semiconductor corporation www.fairchildsemi.com fsusb11 ? rev. 1.0.4 3 fsusb11 ? low-power, full-speed (12mbps) switch absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v cc supply voltage -0.5 6.0 v v s switch voltage -0.5 v cc + 0.5 v v in input voltage (1) -0.5 6.0 v i ik input diode current -50 ma i sw switch current 200 ma i swpeak peak switch current (pulsed at 1ms duration, <10% duty cycle) 400 ma t stg storage temperature range -65 +150 c t j maximum junction temperature +150 c t l lead temperature (soldering, 10 seconds) +260 c esd human body model, jesd22-a114 8 kv note : 1. the input and output negative voltage ratings may be ex ceeded if the input and output diode current ratings are observed. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. max. unit v cc power supply 1.65 5.50 v v in control input voltage (2) 0 v cc v cc v sw switch input voltage 0 v cc v cc t a operating temperature -40 +85 c note : 2. unused inputs must be held high or low. they may not float.
? 2005 fairchild semiconductor corporation www.fairchildsemi.com fsusb11 ? rev. 1.0.4 4 fsusb11 ? low-power, full-speed (12mbps) switch dc electrical characteristics unless otherwise specified, typical values are at +25c. symbol parameter conditions v cc (v) t a =+25c t a =-40 to +85c units min. typ. max. min. max. v ih input voltage high 2.7 to 3.6 2.0 v 4.5 to 5.5 4.0 v il input voltage low 2.7 to 3.6 v 4.5 to 5.5 i in control input leakage v in =0v to v cc 2.7 to 3.6 a 4.5 to 5.5 i no(off), i no(off) off-leakage current of port d 1 and d 2 a=1v, 4.5v, b 0 or b 1 =1v, 4.5v 5.5 -50 50 -100 100 na i a(on) on-leakage current of port d a=1v, 4.5v, b 0 or b 1 =1v, 4.5v or floating 5.5 50 50 -100 100 na r on switch on resistance (3) micropak i out = 100ma, d 1 or d 2 =1.5v 2.7 2.60 4.00 4.30 i out = 100ma, d 1 or d 2 =3.5v 4.5 0.95 1.15 1.30 tssop i out = 100ma, d 1 or d 2 =1.5v 2.7 2.80 4.50 i out = 100ma, d 1 or d 2 =3.5v 4.5 1.50 3.00 r on on resistance matching between channel (4) micropak i out = 100ma, d 1 or d 2 =3.5v 4.5 0.06 0.12 0.15 tssop 0.07 0.30 r flat(on) on resistance flatness (5) i out =100ma, d 1 or d 2 =0v, 0.75v, 1.5v 2.7 1.4 i out =100ma, b 0 or b 1 =0v, 1v, 2v 4.5 0.2 0.3 0.4 i cc quiescent supply current v in =0v or v cc , i out =0 3.6 0.1 0.5 1.0 a 5.5 0.1 0.5 1.0 notes : 3. on resistance is determined by the voltage drop betw een d and dn pins at the indicated current through the switch. 4. r on = r onmax - r onmin measured at identical v cc , temperature, and voltage. 5. flatness is defined as the difference between the maximum and minimum value of on resistance over the specified range of conditions.
? 2005 fairchild semiconductor corporation www.fairchildsemi.com fsusb11 ? rev. 1.0.4 5 fsusb11 ? low-power, full-speed (12mbps) switch ac electrical characteristics unless otherwise specified, typical values are at +25c. symbol parameter conditions v cc (v) t a =+25c t a =-40 to +85c units figure min. typ. max. min. max. t on turn-on time s-to-bus b d 1 or d 2 =1.5v, r l =50 , c l =35pf 2.7 to 3.6 50 60 ns figure 5 d 1 or d 2 =3.0v, r l =50 , c l =35pf 4.5 to 5.5 35 30 t off turn-off time s-to-bus b d 1 or d 2 =1.5v, r l =50 , c l =35pf 2.7 to 3.6 20 20 ns figure 5 d 1 or d 2 =3.0v, r l =50 , c l =35pf 4.5 to 5.5 15 t bbm break-before-make time d 1 or d 2 =1.5v, r l =50 , c l =35pf 2.7 to 3.6 1 ns figure 6 d 1 or d 2 =3.0v, r l =50 , c l =35pf 4.5 to 5.5 20 1 q charge injection c l =1.0nf, v gen =0v, r gen =0 2.7 to 3.6 20 pc figure 8 4.5 to 5.5 10 o irr off isolation f=1mhz, r l =50 2.7 to 3.6 -70 db figure 7 4.5 to 5.5 -70 x talk non-adjacent channel crosstalk f=1mhz, r l =50 2.7 to 3.6 -75 db figure 7 4.5 to 5.5 -75 bw -3db bandwidth r l =50 2.7 to 3.6 350 mhz figure 10 4.5 to 5.5 350 usb related ac electrical characteristics unless otherwise specified, typical values are at 25c. symbol parameter conditions v cc (v) t a =+25c units figure min. typ. max. t sk(o) skew r s =39, c l =50pf, t r =t f =12ns at 12mbps 2.7 to 3.6 0.15 ns figure 11 4.5 to 5.5 0.15 t sk(p) rising/fall time mismatch (duty cycle=50%) 2.7 to 3.6 30 ps figure 12 4.5 to 5.5 20 t j total jitter r s =39, c l =50pf, t r =t f =12ns at 12mbps (prbs=2 15 1) 2.7 to 3.6 1.7 ps figure 12 4.5 to 5.5 1.6 capacitance symbol parameter conditions v cc (v) t a =+25c units figure min. typ. max. c in control pin input capacitance f=1mhz 0.0 3.5 pf figure 9 c off d n port off capacitance f=1mhz 4.5 12.0 pf figure 9 c on d port on capacitance f=1mhz 4.5 40.0 pf figure 9
? 2005 fairchild semiconductor corporation www.fairchildsemi.com fsusb11 ? rev. 1.0.4 6 fsusb11 ? low-power, full-speed (12mbps) switch ac loadings and waveforms note: 6. cl includes fixture and stray capacitance. note: 7. logic input waveforms inverted for switches that have the opposite logic sense. figure 5. turn on/ turn off timing note: 8. c l includes fixture and stray capacitance. figure 6. break-before-make timing figure 7. off isolation and crosstalk
? 2005 fairchild semiconductor corporation www.fairchildsemi.com fsusb11 ? rev. 1.0.4 7 fsusb11 ? low-power, full-speed (12mbps) switch ac loadings and waveforms (continued) note: 9. q=( v out ) (c l ). figure 8. charge injection figure 9. on/off capacitance measurement setup figure 10. bandwidth figure 11. skew test figure 12. rise/fall time mismatch test
? 2005 fairchild semiconductor corporation www.fairchildsemi.com fsusb11 ? rev. 1.0.4 8 fsusb11 ? low-power, full-speed (12mbps) switch physical dimensions bottom view top view recommended land pattern side view 2x 2x notes: a. package conforms to jedec registration mo-255, variation uabd . b. dimensions are in millimeters. c. dimensions and tolerances per asme y14.5m, 1994. d. presence of center pad is package supplier dependent. if present it is not intended to be soldered and has a black oxide finish. e. drawing filename: mkt-mac10arev5. 0.10 c 0.10 c 0.10 cab 0.05 c pin1 ident is 2x longer than other lines a b c 0.35 0.25 9x 9x 14 9 6 0.25 0.15 10 5 0.50 0.56 1.62 0.05 0.00 0.05 c 0.55 max 0.05 c 1.60 2.10 (0.35) (0.25) 0.50 10x 10x (0.11) 1.12 1.62 keepout zone, no traces or vias allowed (0.20) (0.15) 0.35 0.25 0.35 0.25 detail a detail a 2x scale 0.35 0.25 0.65 0.55 d all features (0.36) (0.29) 0.56 figure 13. 10-lead, micropak?, jedec mo255,1.6 x 2.1mm package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . tape and reel specification please visit fairchild semiconductor?s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf . package designator tape section cavity number cavity status cover type status l10x leader (start end) 125 (typical) empty sealed carrier 5000 filled sealed trailer (hub end) 75 (typical) empty sealed
? 2005 fairchild semiconductor corporation www.fairchildsemi.com fsusb11 ? rev. 1.0.4 9 fsusb11 ? low-power, full-speed (12mbps) switch physical dimensions c. dimensions are exclusive of burrs, mold flash, and tie bar extrusions f. drawing file name: mtc14rev6 r0.09 min 12.00 top & bottom 0.43 typ 1.00 d. dimensioning and tolerances per ansi y14.5m, 1982 r0.09min e. landpattern standard: sop65p640x110-14m 0.65 6.10 1.65 0.45 a. conforms to jedec registration mo-153, variation ab, ref note 6 b. dimensions are in millimeters figure 14. 14-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/
? 2005 fairchild semiconductor corporation www.fairchildsemi.com fsusb11 ? rev. 1.0.4 10 fsusb11 ? low-power, full-speed (12mbps) switch
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